Condor Currents

Condor Computing · s3.us-east-2.amazonaws.com

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

122 episodes

8d ago latest

5x a week cadence

English language

▶ Play latestRSS feed Website Technology News

https://limitless-ai-podcasts.s3.us-east-2.amazonaws.com/condor-currents/rss.xml

Episodes 130

NOVA: Technology-Architecture Co-Design of Near-Memory Processing for Attention-SSM-MoE Hybrid LLM Inference
20h ago
## Episode Summary In this episode, we cover: - **NOVA: Technology-Architecture Co-Design of Near-Memory Processing for Attention-SSM-MoE Hybrid LLM Inference** (arXiv) - **Performance Foundations of Parallel & Distributed Reasoning Language Models** (arXiv) - **Nvidia Vera CPU Architecture: Max single-threaded CPU at scale for agents - GamesBeat** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC - HPCwir
SILK: Closing the Time-of-Check-to-Time-of-Use Gap in RoT-Protected AI Systems
yesterday
## Episode Summary In this episode, we cover: - **SILK: Closing the Time-of-Check-to-Time-of-Use Gap in RoT-Protected AI Systems** (arXiv) - **Simthesizer: An Agent-Driven Simulation Framework for LLM Serving Systems** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - nature.com** (google_riscv) - **Enabling Comprehensive CWE-based Assurance for RISC-V Processors - Semiconductor Engineering** (google_riscv) - **Milk-V Jupiter2 is mini PC with a SpacemiT K3 RISC-V processor - Liliputing** (google_riscv) --- *Sponsored by Ada, Ago Consulting,
PRO-RAN: Processor-Level Characterization of Open RAN Centralized and Distributed Units
2d ago
## Episode Summary In this episode, we cover: - **PRO-RAN: Processor-Level Characterization of Open RAN Centralized and Distributed Units** (arXiv) - **FoldPipe: Bounded Remote Streaming of Native Molecular Shards with Asynchronous Prefetch** (arXiv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **SpacemiT to launch server-class RISC-V processor following capital injection - South China Morning Post** (google_riscv) - **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_ris
FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration
3d ago
## Episode Summary In this episode, we cover: - **FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration** (arXiv) - **Squeezing the Cache, Preserving the Truth: Monotonic Equipotential Allocation with Geodesia-KV** (arXiv) - **How Cache Coherency Simplifies AI Software** (semiengineering) - **Arm Reveals AGI Server CPU Architecture at Hot Chips, Targeting Agentic AI Workloads - finance.biggo.com** (google_arch) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) --- *Sponsored by Ada, Ago Con
Pipeline-Native Transformers: Co-Designing Model Architecture and CPU Inference for Bandwidth-Efficient Autoregressive Decode
4d ago
## Episode Summary In this episode, we cover: - **Pipeline-Native Transformers: Co-Designing Model Architecture and CPU Inference for Bandwidth-Efficient Autoregressive Decode** (arXiv) - **Elastic KV Cache for LLM Serving:A Working Reclamation Mechanism, and Why Chunked Prefill Already Closes the Gap** (arXiv) - **Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V - Nature** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit** (google_riscv) - **Armaan Gomes and Friends Deliver Playable Doom on a Whole New Plat
Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era
5d ago
## Episode Summary In this episode, we cover: - **Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era** (arXiv) - **TreeWY: Speculative Verification for Gated DeltaNet Hybrids** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **RISC-V extensions for high performance embedded computing ... - eeNews Europe** (google_riscv) - **RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 - Phoronix** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration
6d ago
## Episode Summary In this episode, we cover: - **SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration** (arXiv) - **Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **StarFive Dubhe-100 – A 64-bit, RVA23-compliant RISC-V core for high-performance applications - CNX Software** (google_riscv) - **StarFive Targets High-Performance Compute Workloads with Its New Dubh
Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics
7d ago
## Episode Summary In this episode, we cover: - **Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics** (arXiv) - **Beyond Binary Priorities: Multi-Tier SLA Scheduling for Large Language Model Serving** (arXiv) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **Linux Kernel 7.2 Officially Released with Cache-Aware Scheduling, USB4STREAM, and Major AMD Improvements - Linux Journ
From Retrieved Context to Runtime Control: Adaptive Compression for Edge-based RAG
8d ago
## Episode Summary In this episode, we cover: - **From Retrieved Context to Runtime Control: Adaptive Compression for Edge-based RAG** (arXiv) - **DTX: A Throughput-First Training Accelerator for Diffusion and Transformer Models** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconduc
A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation
9d ago
## Episode Summary In this episode, we cover: - **A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation** (arXiv) - **Performance Verification of the AmpereOne CPU Core** (arXiv) - **Intel says Nova Lake, its next major CPU architecture, is coming to desktop PCs before servers - TechSpot** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck** (google_arch) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) --- *Sponsored by Ada
FPGA Lifecycle Management for RISC-V Systems
10d ago
## Episode Summary In this episode, we cover: - **FPGA Lifecycle Management for RISC-V Systems** (arXiv) - **CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
ETHEREAL: A 25.6-$μ$s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge
11d ago
## Episode Summary In this episode, we cover: - **ETHEREAL: A 25.6-$μ$s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge** (arXiv) - **Dryas: A Reprogrammable Engine for High-Speed Interconnect Tracing and Analysis** (arXiv) - **The RISC-V Vector Extensions for AI - jonpeddie.com** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - wccftech.com** (google_arch) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) --
Testing the EPYC Conjecture on Real Hardware: MoA-Guided Dense Matrix Multiplication on NCSA Delta (AMD EPYC 7763 Milan)
12d ago
## Episode Summary In this episode, we cover: - **Testing the EPYC Conjecture on Real Hardware: MoA-Guided Dense Matrix Multiplication on NCSA Delta (AMD EPYC 7763 Milan)** (arXiv) - **Beyond Capacity: Scalable MoE LLM Inference via High-Bandwidth Flash with Direct GPU and HBM Paths** (arXiv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - techpowerup.com** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Co
SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon
13d ago
## Episode Summary In this episode, we cover: - **SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon** (arXiv) - **Potential Applications of HBF in LLM Serving Systems** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One
14d ago
## Episode Summary In this episode, we cover: - **What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One** (arXiv) - **ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - cnx-software.com** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccft
SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon
15d ago
## Episode Summary In this episode, we cover: - **SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon** (arXiv) - **DistillCache: KL-Guided Adaptive KV-Cache Eviction for Memory-Efficient LLM Inference** (arXiv) - **A Deep Dive Into CPU Architecture - i-programmer.info** (google_arch) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen
Why Do Prefetchers Fail? Let Agents Answer
16d ago
## Episode Summary In this episode, we cover: - **Why Do Prefetchers Fail? Let Agents Answer** (arXiv) - **Machine Shape and Hierarchical Blocking: A Mathematics of Arrays Formalization, with an Open Problem in Hierarchical Shape Occupancy** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - hackaday.com** (google_arch) - **China's LineShine tops supercomputer ranking with all-CPU architecture - chinadaily.com.cn** (google_arch) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - computer.org** (google_arch) ---
APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference
17d ago
## Episode Summary In this episode, we cover: - **APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference** (arXiv) - **Aneto: Predicting System Performance by Exploiting Cross-Workload Regularity** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - design-reuse.com** (google_arch) - **Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW** (riscv_news) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
ArchAgent v2: A Case Study with the Data Prefetching Championship
18d ago
## Episode Summary In this episode, we cover: - **ArchAgent v2: A Case Study with the Data Prefetching Championship** (arXiv) - **The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - onlinelibrary.wiley.com** (google_riscv) - **Chinese Loongson processors have leaky caches, researchers find** (the_register) - **Spectre rears its ugly head again as researchers show some RISC-V chips are susceptible** (the_register) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
21d ago
## Episode Summary In this episode, we cover: - **A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs** (arXiv) - **MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - semiengineering.com** (google_riscv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor
Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention
22d ago
## Episode Summary In this episode, we cover: - **Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention** (arXiv) - **Celty: SpMspV GPU Kernel and SIMT Co-Design for Efficient Dual-Sparse LLM Inference** (arXiv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - notebookcheck.net** (google_arch) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU
PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving
23d ago
## Episode Summary In this episode, we cover: - **PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving** (arXiv) - **Breaking Memory Bottlenecks in Quantum Control Systems for More Precise Experiments and Higher Throughput Computing** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - phoronix.com** (google_riscv) - **Performance aware shared memory hierarchy model for multicore processors - nature.com** (google_arch)
Architectural Implications of Agentic AI Workflows
24d ago
## Episode Summary In this episode, we cover: - **Architectural Implications of Agentic AI Workflows** (arXiv) - **On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (google_arch) - **AMD Zen 6 CPU architecture may include new optimisations to tackle game stutter - kitguru.net** (google_arch) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_arch) --- *Sponsored by Ada, Ago Consulting, and Zen Semiconductor*
LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
25d ago
## Episode Summary In this episode, we cover: - **LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension** (arXiv) - **A Time-Multiplexed Spiking Neural Network Accelerator with Pipelined Readout for FPGA Inference** (arXiv) - **RISC-V vs ARM: Which Instruction Set Architecture Will Dominate the Future? - Electropages** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M.2 and PCIe support launches - Notebookcheck
Themis: Software-Defined Hardware Prefetching
26d ago
## Episode Summary In this episode, we cover: - **Themis: Software-Defined Hardware Prefetching** (arXiv) - **Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies** (arXiv) - **AMD Zen 6 CPU architecture may include new optimisations to tackle game stutter - KitGuru** (google_arch) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System Stacks - IEEE Computer Society** (google_arch) --- *Sponsored by Ada, Ago Consultin

Episodes

Reading the feed…

Also on s3.us-east-2.amazonaws.com

More Technology shows

AppleVis Podcast

applevis.com

810 episodes · 8d ago

Material

relay.fm

582 episodes · 9d ago

Área de Transferência

gigahertz.fm

493 episodes · 8d ago

Super Feed

gigahertz.fm

1,000 episodes · 8d ago

Don't Panic

dontpanic.io

410 episodes · 8d ago

HTML All The Things - Web Development, AI, and Developer Careers

htmlallthethings.com

523 episodes · 8d ago

Condor Currents

Episodes 130

NOVA: Technology-Architecture Co-Design of Near-Memory Processing for Attention-SSM-MoE Hybrid LLM Inference

SILK: Closing the Time-of-Check-to-Time-of-Use Gap in RoT-Protected AI Systems

PRO-RAN: Processor-Level Characterization of Open RAN Centralized and Distributed Units

FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration

Pipeline-Native Transformers: Co-Designing Model Architecture and CPU Inference for Bandwidth-Efficient Autoregressive Decode

Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era

SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration

Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics

From Retrieved Context to Runtime Control: Adaptive Compression for Edge-based RAG

A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation

FPGA Lifecycle Management for RISC-V Systems

ETHEREAL: A 25.6-$μ$s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge

Testing the EPYC Conjecture on Real Hardware: MoA-Guided Dense Matrix Multiplication on NCSA Delta (AMD EPYC 7763 Milan)

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon

What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon

Why Do Prefetchers Fail? Let Agents Answer

APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference

ArchAgent v2: A Case Study with the Data Prefetching Championship

A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs

Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention

PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving

Architectural Implications of Agentic AI Workflows

LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension

Themis: Software-Defined Hardware Prefetching

Episodes

Also on s3.us-east-2.amazonaws.com

AI Special Report

PodBot - Podcast de Tecnologia

Git News AI

Unzip

Funded

The AI Hardware Show

More Technology shows

AppleVis Podcast

Material

Área de Transferência

Super Feed

Don't Panic

HTML All The Things - Web Development, AI, and Developer Careers

Episodes 130

NOVA: Technology-Architecture Co-Design of Near-Memory Processing for Attention-SSM-MoE Hybrid LLM Inference

SILK: Closing the Time-of-Check-to-Time-of-Use Gap in RoT-Protected AI Systems

PRO-RAN: Processor-Level Characterization of Open RAN Centralized and Distributed Units

FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration

Pipeline-Native Transformers: Co-Designing Model Architecture and CPU Inference for Bandwidth-Efficient Autoregressive Decode

Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era

SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration

Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics

From Retrieved Context to Runtime Control: Adaptive Compression for Edge-based RAG

A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation

FPGA Lifecycle Management for RISC-V Systems

ETHEREAL: A 25.6-$μ$s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge

Testing the EPYC Conjecture on Real Hardware: MoA-Guided Dense Matrix Multiplication on NCSA Delta (AMD EPYC 7763 Milan)

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon

What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon

Why Do Prefetchers Fail? Let Agents Answer

APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference

ArchAgent v2: A Case Study with the Data Prefetching Championship

A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs

Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention

PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving

Architectural Implications of Agentic AI Workflows

LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension

Themis: Software-Defined Hardware Prefetching